Many modern computing applications are run at execution platforms employing inexpensive and low-power system-on-chip (SOC) architectures. In an SOC architecture, a number of electronic components including a primary processor or CPU, one or more physical memory devices, graphic processors, audio-visual components and the like are implemented on a single chip substrate. In many cases, the developers of a particular SOC implementation may obtain the primary processor from a third party vendor which specializes in processor design.
For any given processor, the maximum address space (e.g., a 32-bit address space, which corresponds to four gigabytes of addressable memory), which is selected by the processor designers, impacts multiple portions of the design of internal subcomponents of the processor. For example, the design of the instruction and data caches of the processors as well as the memory management unit may be closely tied to the address space limit selected.
In some cases a processor may be used in an SOC which incorporates one or more physical memory devices with larger address spaces than that of the processor itself. For example, it may be possible to include a dynamic random access memory (DRAM) device with a 36-bit address space or a 40-bit address space in an SOC with a processor having a 32-bit address space. For some types of applications, it may be desirable from the perspective of the SOC designers to enable the processor to utilize such larger address ranges. Unfortunately, in many cases, the choices available to such SOC designers may be limited. Given cost and power-related constraints, the SOC designers may not necessarily be able to choose a different processor with a larger address range. Modifying the internal subcomponents of the processor itself to support the memory's address range may be a large and expensive undertaking. Redesigning and re-implementing the processor caches and memory management unit may require substantial design and verification effort, and may also reduce the area available for other SOC components on the chip. In some cases modifying the internal subcomponents of the processor may not even be feasible in view of contractual obligations with the processor vendor. At least some applications which are capable of benefiting from the larger address range of a memory devices of an SOC, but are restricted to utilizing the address range of the processor on the SOC, may exhibit sub-optimal performance.